Vivado HLS Report Comparison for
randombytes_2
General Information
Date:
2/9/2020
Project:
randombytes_2
Product family:
Virtex-7
Target device:
xc7vx485tffg1157-1
Resource Usage estimated post-synthesis
|
Solution Name
|
LUT
|
FF
|
DSP
|
BRAM
|
|
Reference_Version
|
314
|
91
|
0
|
0
|
|
Optimized_version
|
120
|
28
|
0
|
0
|
Performance Estimates
-
Timing
|
Solution Name
|
Clock
|
Target
|
Achieved
|
|
Reference_Version
|
ap_clk
|
6.60 ns
|
4.620 ns
|
|
Optimized_version
|
ap_clk
|
6.60 ns
|
5.544 ns
|
-
Latency
|
Solution Name
|
Latency (cycles)
|
Latency (absolute)
|
|
min
|
max
|
min
|
max
|
|
Reference_Version
|
2
|
5193
|
13.200 ns
|
34.274 us
|
|
Optimized_version
|
2
|
5193
|
13.200 ns
|
34.274 us
|
Timing Details
Solution name : Reference_Version
-
Instances
-
Loops
|
Loop name
|
Latency (cycles)
|
Iteration Latency
|
Trip count
|
|
min
|
max
|
min
|
max
|
min
|
max
|
|
rb2
|
0
|
5191
|
1
|
0
|
5191
|
Solution name : Optimized_version
-
Instances
-
Loops
|
Loop name
|
Latency (cycles)
|
Iteration Latency
|
Trip count
|
|
min
|
max
|
min
|
max
|
min
|
max
|
|
rb2
|
0
|
5191
|
1
|
0
|
5191
|