Vivado HLS Report Comparison for
randombytes_2
General Information
Date:
3/9/2020
Project:
randombytes
Product family:
Virtex-7
Target device:
xc7vx485tffg1157-1
Resource Usage estimated post-synthesis
Solution Name
|
LUT
|
FF
|
DSP
|
BRAM
|
Reference_Version
|
320
|
109
|
0
|
0
|
Optimized_version
|
126
|
46
|
0
|
0
|
Resource Usage measured post-implementation
Solution Name
|
SLICE
|
LUT
|
FF
|
DSP
|
BRAM
|
Reference_Version
|
12
|
19
|
45
|
0
|
0
|
Optimized_version
|
12
|
19
|
45
|
0
|
0
|
Performance Estimates
-
Timing
Solution Name
|
Clock
|
Target
|
Achieved
|
Reference_Version
|
ap_clk
|
6.600 ns
|
2.229 ns
|
Optimized_version
|
ap_clk
|
6.600 ns
|
2.229 ns
|
-
Latency
Solution Name
|
Latency (cycles)
|
Latency (absolute)
|
min
|
max
|
min
|
max
|
Reference_Version
|
2
|
10384
|
13.200 ns
|
68.534 us
|
Optimized_version
|
2
|
10384
|
13.200 ns
|
68.534 us
|
Timing Details
Solution name : Reference_Version
-
Instances
Instance Name
|
Latency (cycles)
|
Latency (absolute)
|
min
|
max
|
min
|
max
|
lfsr_randombytes
|
0
|
0 ns
|
randombytes_2
|
2
|
10384
|
13.200 ns
|
68.534 us
|
-
Loops
Loop name
|
Latency (cycles)
|
Iteration Latency
|
Trip count
|
min
|
max
|
min
|
max
|
min
|
max
|
rb2
|
0
|
10382
|
2
|
0
|
5191
|
Solution name : Optimized_version
-
Instances
Instance Name
|
Latency (cycles)
|
Latency (absolute)
|
min
|
max
|
min
|
max
|
lfsr_randombytes
|
0
|
0 ns
|
randombytes_2
|
2
|
10384
|
13.200 ns
|
68.534 us
|
-
Loops
Loop name
|
Latency (cycles)
|
Iteration Latency
|
Trip count
|
min
|
max
|
min
|
max
|
min
|
max
|
rb2
|
0
|
10382
|
2
|
0
|
5191
|